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GLVLSI
2007
IEEE
173views VLSI» more  GLVLSI 2007»
14 years 12 months ago
Modeling and estimating leakage current in series-parallel CMOS networks
This paper reviews the modeling of subthreshold leakage current and proposes an improved model for general series-parallel CMOS networks. The presence of on-switches in off-networ...
Paulo F. Butzen, André Inácio Reis, ...
104
Voted
SIAMSC
2010
151views more  SIAMSC 2010»
14 years 10 months ago
An Adaptive Finite Element Method for the Eddy Current Model with Circuit/Field Couplings
We develop an adaptive finite element method for solving the eddy current model with voltage excitations for complicated three dimensional structures. The mathematical model is ba...
Junqing Chen, Zhiming Chen, Tao Cui, Lin-Bo Zhang
ISQED
2006
IEEE
142views Hardware» more  ISQED 2006»
15 years 5 months ago
Constructing Current-Based Gate Models Based on Existing Timing Library
Current-based gate modeling achieves a new level of accuracy in nanoscale design timing and signal integrity analysis. However, to generate current-based gate models requires addi...
Andrew B. Kahng, Bao Liu, Xu Xu
DATE
2009
IEEE
87views Hardware» more  DATE 2009»
15 years 6 months ago
Efficient compression and handling of current source model library waveforms
—This paper describes a waveform compression technique suitable for the efficient utilization, storage and interchange of the emerging current source model (CSM) based cell libra...
Safar Hatami, Peter Feldmann, Soroush Abbaspour, M...
PATMOS
2005
Springer
15 years 5 months ago
A New Model for Timing Jitter Caused by Device Noise in Current-Mode Logic Frequency Dividers
A new method for predicting timing jitter caused by device noise in current-mode logic (CML) frequency dividers is presented. Device noise transformation into jitter is modeled as ...
Marko Aleksic, Nikola Nedovic, K. Wayne Current, V...