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ISCAS
2003
IEEE
172views Hardware» more  ISCAS 2003»
15 years 3 months ago
Performance modeling of resonant tunneling based RAMs
Tunneling based random-access memories (TRAM’s) have recently garnered a great amount of interests among the memory designers due to their intrinsic merits such as reduced power...
Hui Zhang, Pinaki Mazumder, Li Ding 0002, Kyoungho...
IPPS
2002
IEEE
15 years 2 months ago
Real-Time Communication for Distributed Vision Processing Based on Imprecise Computation Model
In this paper we propose an efficient real-time communication mechanism for distributed vision processing. One of the biggest problems of distributed vision processing, as is the ...
Hiromasa Yoshimoto, Daisaku Arita, Rin-ichiro Tani...
ICASSP
2011
IEEE
14 years 1 months ago
A methodology based on Transportation problem modeling for designing parallel interleaver architectures
For high-data-rate applications, turbo-like iterative decoders are implemented with parallel hardware architecture. However, to achieve high throughput, concurrent accesses to each...
Awais Sani, Philippe Coussy, Cyrille Chavet, Eric ...
ICDCS
2006
IEEE
15 years 4 months ago
Sharing Memory between Byzantine Processes using Policy-Enforced Tuple Spaces
Despite the large amount of Byzantine fault-tolerant algorithms for message-passing systems designed through the years, only recently algorithms for the coordination of processes ...
Alysson Neves Bessani, Joni da Silva Fraga, Miguel...
RIAO
2004
14 years 11 months ago
Group Memory Based on the Task Information
A group memory of a project is an information space storing the documents produced and exchanged by members of the group, which may include the electronic discussions that took pl...
Jonathan Yu, James A. Thom, Leila Alem