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ISCAS
2002
IEEE
124views Hardware» more  ISCAS 2002»
15 years 2 months ago
Performance optimization of multiple memory architectures for DSP
Multiple memory module architecture offers higher performance by providing potentially doubled memory bandwidth. Two key problems in gaining high performance in this kind of archi...
Qingfeng Zhuge, Bin Xiao, Edwin Hsing-Mean Sha
CODES
2000
IEEE
15 years 2 months ago
Memory architecture for efficient utilization of SDRAM: a case study of the computation/memory access trade-off
This paper discusses the trade-off between calculations and memory accesses in a 3D graphics tile renderer for visualization of data from medical scanners. The performance require...
Thomas Gleerup, Hans Holten-Lund, Jan Madsen, Stee...
ICS
1999
Tsinghua U.
15 years 2 months ago
Nonlinear array layouts for hierarchical memory systems
Programming languages that provide multidimensional arrays and a flat linear model of memory must implement a mapping between these two domains to order array elements in memory....
Siddhartha Chatterjee, Vibhor V. Jain, Alvin R. Le...
COLT
2006
Springer
15 years 1 months ago
Memory-Limited U-Shaped Learning
U-shaped learning is a learning behaviour in which the learner first learns a given target behaviour, then unlearns it and finally relearns it. Such a behaviour, observed by psych...
Lorenzo Carlucci, John Case, Sanjay Jain, Frank St...
NIPS
2003
14 years 11 months ago
Dopamine Modulation in a Basal Ganglio-cortical Network Implements Saliency-based Gating of Working Memory
Dopamine exerts two classes of effect on the sustained neural activity in prefrontal cortex that underlies working memory. Direct release in the cortex increases the contrast of p...
Aaron J. Gruber, Peter Dayan, Boris S. Gutkin, Sar...