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TACAS
2010
Springer
210views Algorithms» more  TACAS 2010»
15 years 4 months ago
Automatic Analysis of Scratch-Pad Memory Code for Heterogeneous Multicore Processors
Modern multicore processors, such as the Cell Broadband Engine, achieve high performance by equipping accelerator cores with small “scratchpad” memories. The price for increase...
Alastair F. Donaldson, Daniel Kroening, Philipp R&...
DATE
2005
IEEE
135views Hardware» more  DATE 2005»
15 years 3 months ago
Compositional Memory Systems for Multimedia Communicating Tasks
Conventional cache models are not suited for real-time parallel processing because tasks may flush each other’s data out of the cache in an unpredictable manner. In this way th...
Anca Mariana Molnos, Marc J. M. Heijligers, Sorin ...
ISCA
2005
IEEE
101views Hardware» more  ISCA 2005»
15 years 3 months ago
Virtualizing Transactional Memory
Writing concurrent programs is difficult because of the complexity of ensuring proper synchronization. Conventional lock-based synchronization suffers from wellknown limitations, ...
Ravi Rajwar, Maurice Herlihy, Konrad K. Lai
IPPS
2003
IEEE
15 years 3 months ago
Global Communication Optimization for Tensor Contraction Expressions under Memory Constraints
The accurate modeling of the electronic structure of atoms and molecules involves computationally intensive tensor contractions involving large multi-dimensional arrays. The effi...
Daniel Cociorva, Xiaoyang Gao, Sandhya Krishnan, G...
IPPS
2005
IEEE
15 years 3 months ago
EMPS: An Environment for Memory Performance Studies
This paper describes an overview of Environment for Memory Performance Studies (EMPS). EMPS is a framework to allow different data gathering and simulation tools to be composed to...
Jeffrey K. Hollingsworth, Allan Snavely, Simone Sb...