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ISCA
1998
IEEE
125views Hardware» more  ISCA 1998»
15 years 1 months ago
Active Pages: A Computation Model for Intelligent Memory
Microprocessors and memory systems su er from a growing gap in performance. We introduce Active Pages, a computation model which addresses this gap by shifting data-intensive comp...
Mark Oskin, Frederic T. Chong, Timothy Sherwood
ISCA
2009
IEEE
239views Hardware» more  ISCA 2009»
15 years 4 months ago
Scalable high performance main memory system using phase-change memory technology
The memory subsystem accounts for a significant cost and power budget of a computer system. Current DRAM-based main memory systems are starting to hit the power and cost limit. A...
Moinuddin K. Qureshi, Vijayalakshmi Srinivasan, Ju...
IPPS
2003
IEEE
15 years 3 months ago
Model Checking a Cache Coherence Protocol for a Java DSM Implementation
Jackal is a fine-grained distributed shared memory implementation of the Java programming language. It aims to implement Java’s memory model and allows multithreaded Java progr...
Jun Pang, Wan Fokkink, Rutger F. H. Hofman, Ronald...
SIAMCOMP
2008
154views more  SIAMCOMP 2008»
14 years 8 months ago
Cryptography in the Bounded-Quantum-Storage Model
We initiate the study of two-party cryptographic primitives with unconditional security, assuming that the adversary's quantum memory is of bounded size. We show that oblivio...
Ivan Damgård, Serge Fehr, Louis Salvail, Chr...
VLSID
2007
IEEE
130views VLSI» more  VLSID 2007»
15 years 10 months ago
Memory Architecture Exploration for Power-Efficient 2D-Discrete Wavelet Transform
The Discrete Wavelet Transform (DWT) forms the core of the JPEG2000 image compression algorithm. Since the JPEG2000 compression application is heavily data-intensive, the overall ...
Rahul Jain, Preeti Ranjan Panda