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CAV
1998
Springer
175views Hardware» more  CAV 1998»
15 years 2 months ago
An ACL2 Proof of Write Invalidate Cache Coherence
As a pedagogical exercise in ACL2, we formalize and prove the correctness of a write invalidate cache scheme. In our formalization, an arbitrary number of processors, each with its...
J. Strother Moore
TACAS
1998
Springer
81views Algorithms» more  TACAS 1998»
15 years 2 months ago
Formal Design and Analysis of a Gear Controller
In this paper, we report on an application of the validation and veri cation tool kit Uppaal in the design and analysis of a prototype gear controller, carried out in a joint proje...
Magnus Lindahl, Paul Pettersson, Wang Yi
VLDB
1998
ACM
180views Database» more  VLDB 1998»
15 years 2 months ago
Active Storage for Large-Scale Data Mining and Multimedia
The increasing performance and decreasing cost of processors and memory are causing system intelligence to move into peripherals from the CPU. Storage system designers are using t...
Erik Riedel, Garth A. Gibson, Christos Faloutsos
SPAA
1993
ACM
15 years 1 months ago
Supporting Sets of Arbitrary Connections on iWarp Through Communication Context Switches
In this paper we introduce the ConSet communication model for distributed memory parallel computers. The communication needs of an application program can be satisfied by some ar...
Anja Feldmann, Thomas Stricker, Thomas E. Warfel
AUSAI
2006
Springer
15 years 1 months ago
Robust Character Recognition Using a Hierarchical Bayesian Network
There is increasing evidence to suggest that the neocortex of the mammalian brain does not consist of a collection of specialised and dedicated cortical architectures, but instead ...
John Thornton, Torbjorn Gustafsson, Michael Blumen...