As a pedagogical exercise in ACL2, we formalize and prove the correctness of a write invalidate cache scheme. In our formalization, an arbitrary number of processors, each with its...
In this paper, we report on an application of the validation and veri cation tool kit Uppaal in the design and analysis of a prototype gear controller, carried out in a joint proje...
The increasing performance and decreasing cost of processors and memory are causing system intelligence to move into peripherals from the CPU. Storage system designers are using t...
In this paper we introduce the ConSet communication model for distributed memory parallel computers. The communication needs of an application program can be satisfied by some ar...
There is increasing evidence to suggest that the neocortex of the mammalian brain does not consist of a collection of specialised and dedicated cortical architectures, but instead ...
John Thornton, Torbjorn Gustafsson, Michael Blumen...