32 search results - page 6 / 7 » Modeling Multiprocessor Cache Protocol Impact on MPI Perform... |
HPCA
2005
IEEE
15 years 9 months ago
2005
IEEE
With the increasing concern of the security on high performance multiprocessor enterprise servers, more and more effort is being invested into defending against various kinds of a...
CONEXT
2007
ACM
15 years 1 months ago
2007
ACM
Very recent activities in the IETF and in the Routing Research Group (RRG) of the IRTG focus on defining a new Internet architecture, in order to solve scalability issues related ...
MICRO
2009
IEEE
15 years 4 months ago
2009
IEEE
Hardware support for dynamic analysis can minimize the performance overhead of useful applications such as security checks, debugging, and profiling. To eliminate implementation ...
HPCA
2005
IEEE
15 years 9 months ago
2005
IEEE
Improvements in semiconductor technology now enable Chip Multiprocessors (CMPs). As many future computer systems will use one or more CMPs and support shared memory, such systems ...
ISCA
2010
IEEE
14 years 11 months ago
2010
IEEE
Two broad classes of memory models are available today: models with hardware cache coherence, used in conventional chip multiprocessors, and models that rely upon software to mana...