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DSN
2002
IEEE
15 years 11 months ago
Model Checking Performability Properties
Model checking has been introduced as an automated technique to verify whether functional properties, expressed in a formal logic like computational tree logic (CTL), do hold in a...
Boudewijn R. Haverkort, Lucia Cloth, Holger Herman...
CGO
2006
IEEE
16 years 17 days ago
Constructing Virtual Architectures on a Tiled Processor
As the amount of available silicon resources on one chip increases, we have seen the advent of ever increasing parallel resources integrated on-chip. Many architectures use these ...
David Wentzlaff, Anant Agarwal
IPPS
2005
IEEE
16 years 3 days ago
Using Message-Driven Objects to Mask Latency in Grid Computing Applications
One of the attractive features of Grid computing is that resources in geographically distant places can be mobilized to meet computational needs as they arise. A particularly chal...
Gregory A. Koenig, Laxmikant V. Kalé
CF
2009
ACM
16 years 1 months ago
Scheduling dynamic parallelism on accelerators
Resource management on accelerator based systems is complicated by the disjoint nature of the main CPU and accelerator, which involves separate memory hierarhcies, different degr...
Filip Blagojevic, Costin Iancu, Katherine A. Yelic...
IEEEPACT
1998
IEEE
15 years 10 months ago
Origin 2000 Design Enhancements for Communication Intensive Applications
The SGI Origin 2000 is designedto support a wide range of applications and has low local and remote memory latencies. However, it often has a high ratio of remote to local misses....
Gheith A. Abandah, Edward S. Davidson