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139
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IPPS
2005
IEEE
15 years 10 months ago
Technology-based Architectural Analysis of Operand Bypass Networks for Efficient Operand Transport
As semiconductor feature sizes decrease, interconnect delay is becoming a dominant component of processor cycle times. This creates a critical need to shift microarchitectural des...
Hongkyu Kim, D. Scott Wills, Linda M. Wills
IPPS
2003
IEEE
15 years 10 months ago
Simulation of Dynamic Data Replication Strategies in Data Grids
Data Grids provide geographically distributed resources for large-scale data-intensive applications that generate large data sets. However, ensuring efficient access to such huge...
Houda Lamehamedi, Zujun Shentu, Boleslaw K. Szyman...
118
Voted
CLUSTER
2009
IEEE
15 years 9 months ago
Finding a tradeoff between host interrupt load and MPI latency over Ethernet
—Achieving high-performance message passing on top of generic ETHERNET hardware suffers from the NIC interruptdriven model where coalescing is usually involved. We present an in-...
Brice Goglin, Nathalie Furmento
129
Voted
IPPS
2000
IEEE
15 years 9 months ago
Using Switch Directories to Speed Up Cache-to-Cache Transfers in CC-NUMA Multiprocessors
In this paper, we propose a novel hardware caching technique, called switch directory, to reduce the communication latency in CC-NUMA multiprocessors. The main idea is to implemen...
Ravi R. Iyer, Laxmi N. Bhuyan, Ashwini K. Nanda
111
Voted
AGENTS
2000
Springer
15 years 9 months ago
Dataflow plan execution for software agents
Recent research has made it possible to build information agents that retrieve and integrate information from the World Wide Web. Although there now exist solutions for modeling W...
Greg Barish, Dan DiPasquo, Craig A. Knoblock, Stev...