78 search results - page 15 / 16 » Modeling QCA for area minimization in logic synthesis |
140
Voted
DAC
2003
ACM
16 years 2 months ago
2003
ACM
Widespread adoption of reconfigurable devices requires system level synthesis techniques to take an application written in a high level language and map it to the reconfigurable d...
81
Voted
ISLPED
2006
ACM
15 years 7 months ago
2006
ACM
This paper addresses the problem of low-power fanout optimization. We show that due to neglecting short-circuit current, previous analytical techniques proposed to optimize the ar...
VLSID
2005
IEEE
16 years 2 months ago
2005
IEEE
We propose a method to minimize power dissipation in current-mode CMOS analog and multiple-valued logic (MVL) circuits employing a stack of current comparators. First, we present ...
120
Voted
ICCAD
1994
IEEE
15 years 6 months ago
1994
IEEE
A simple extension of the critical path method is presented which allows more accurate optimization of circuits with level-sensitive latches. The extended formulation provides a s...
135
click to vote
ISQED
2005
IEEE
15 years 7 months ago
2005
IEEE
As technology continues to scale beyond 100nm, there is a significant increase in performance uncertainty of CMOS logic due to process and environmental variations. Traditional c...