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» Modeling TCP Latency
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112
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DAC
2010
ACM
15 years 7 months ago
Trace-driven optimization of networks-on-chip configurations
Networks-on-chip (NoCs) are becoming increasingly important in general-purpose and application-specific multi-core designs. Although uniform router configurations are appropriate ...
Andrew B. Kahng, Bill Lin, Kambiz Samadi, Rohit Su...
129
Voted
ICCD
2006
IEEE
182views Hardware» more  ICCD 2006»
16 years 19 days ago
A performance and power analysis of WK-Recursive and Mesh Networks for Network-on-Chips
—Network-on-Chip (NoC) has been proposed as an attractive alternative to traditional dedicated wires to achieve high performance and modularity. Power efficiency is one of the mo...
Dara Rahmati, Abbas Eslami Kiasari, Shaahin Hessab...
IPPS
2002
IEEE
15 years 8 months ago
Next Generation System Software for Future High-End Computing Systems
Future high-end computers will offer great performance improvements over today’s machines, enabling applications of far greater complexity. However, designers must solve the cha...
Guang R. Gao, Kevin B. Theobald, Ziang Hu, Haiping...
ESA
2008
Springer
102views Algorithms» more  ESA 2008»
15 years 4 months ago
RFQ: Redemptive Fair Queuing
Fair-queuing schedulers provide clients with bandwidth or latency guarantees provided they are well-behaved i.e. the requested service is always within strict predefined limits. V...
Ajay Gulati, Peter J. Varman
COMCOM
2006
93views more  COMCOM 2006»
15 years 3 months ago
On scalability properties of the Hi3 control plane
The Host Identity Indirection Infrastructure (Hi3) is a general-purpose networking architecture, derived from the Internet Indirection Infrastructure (i3) and the Host Identity Pr...
Dmitry Korzun, Andrei Gurtov