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MICRO
2009
IEEE
160views Hardware» more  MICRO 2009»
15 years 5 months ago
Variation-tolerant non-uniform 3D cache management in die stacked multicore processor
Process variations in integrated circuits have significant impact on their performance, leakage and stability. This is particularly evident in large, regular and dense structures...
Bo Zhao, Yu Du, Youtao Zhang, Jun Yang 0002
NOCS
2007
IEEE
15 years 5 months ago
On Characterizing Performance of the Cell Broadband Engine Element Interconnect Bus
Abstract – With the rise of multicore computing, the design of onchip networks (or networks on chip) has become an increasingly important component of computer architecture. The ...
Thomas William Ainsworth, Timothy Mark Pinkston
MICRO
2006
IEEE
145views Hardware» more  MICRO 2006»
15 years 5 months ago
Virtually Pipelined Network Memory
We introduce virtually-pipelined memory, an architectural technique that efficiently supports high-bandwidth, uniform latency memory accesses, and high-confidence throughput eve...
Banit Agrawal, Timothy Sherwood
ISLPED
2004
ACM
137views Hardware» more  ISLPED 2004»
15 years 4 months ago
Location cache: a low-power L2 cache system
While set-associative caches incur fewer misses than directmapped caches, they typically have slower hit times and higher power consumption, when multiple tag and data banks are p...
Rui Min, Wen-Ben Jone, Yiming Hu
SIGCOMM
2004
ACM
15 years 4 months ago
Vivaldi: a decentralized network coordinate system
Large-scale Internet applications can benefit from an ability to predict round-trip times to other hosts without having to contact them first. Explicit measurements are often un...
Frank Dabek, Russ Cox, M. Frans Kaashoek, Robert M...