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ISCAS
2005
IEEE
124views Hardware» more  ISCAS 2005»
15 years 4 months ago
Parallel FFT computation with a CDMA-based network-on-chip
— Fast Fourier transform (FFT) algorithms are used in a wide variety of digital signal processing applications and many of these require high-performance parallel implementations...
Daewook Kim, Manho Kim, Gerald E. Sobelman
112
Voted
PET
2005
Springer
15 years 4 months ago
An Analysis of Parallel Mixing with Attacker-Controlled Inputs
Parallel mixing [7] is a technique for optimizing the latency of a synchronous re-encryption mix network. We analyze the anonymity of this technique when an adversary can learn the...
Nikita Borisov
91
Voted
SAMOS
2005
Springer
15 years 4 months ago
Automatic FIR Filter Generation for FPGAs
This paper presents a new tool for the automatic generation of highly parallelized Finite Impulse Response (FIR) filters. In this approach we follow our PARO design methodology. P...
Holger Ruckdeschel, Hritam Dutta, Frank Hannig, J&...
97
Voted
DATE
2002
IEEE
114views Hardware» more  DATE 2002»
15 years 3 months ago
A Video Compression Case Study on a Reconfigurable VLIW Architecture
In this paper, we investigate the benefits of a flexible, application-specific instruction set by adding a run-time Reconfigurable Functional Unit (RFU) to a VLIW processor. Preli...
Davide Rizzo, Osvaldo Colavin
92
Voted
IEEEPACT
2002
IEEE
15 years 3 months ago
Efficient Interconnects for Clustered Microarchitectures
Clustering is an effective microarchitectural technique for reducing the impact of wire delays, the complexity, and the power requirements of microprocessors. In this work, we inv...
Joan-Manuel Parcerisa, Julio Sahuquillo, Antonio G...