As CPUs become more powerful with Moore’s law and memory latencies stay constant, the impact of the memory access performance bottleneck continues to grow on relational operator...
With current FPGAs, designers can now instantiate several embedded processors, memory units, and a wide variety of IP blocks to build a single-chip, high-performance multiprocesso...
Metacomputing infrastructures couple multiple clusters (or MPPs) via wide-area networks. A major problem in programming parallel applications for such platforms is their hierarchi...
In this paper we present an analytical-based framework for parallel program performance prediction. The main thrust of this work is to provide a means for treating realistic appli...
The management of one-to-one business interaction is challenged by the latency in the acquisition of information about the individual customer's preferences. Although sharing ...
Barbara Negro, Angelo Difino, Fabio Bellifemine, G...