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115
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MASCOTS
2010
15 years 5 months ago
2010
In this work the authors present an analytical model that -- compared to previously published work -- more accurately captures the delay of IEEE 802.11 protocol under low, medium,...
149
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RTS
2006
15 years 3 months ago
2006
Estimating the Worst Case Execution Time (WCET) of a program on a given processor is important for the schedulability analysis of real-time systems. WCET analysis techniques typic...
115
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DATE
2006
IEEE
15 years 10 months ago
2006
IEEE
Multitasking on reconfigurable logic can achieve very high silicon reusability. However, configuration latency is a major limitation and it can largely degrade the system performa...
127
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IEEEHPCS
2010
15 years 2 months ago
2010
Network-on-chip (NoC) architectures adopted for Systemon-Chip (SoC) are characterized by different trade-offs between latency, throughput, communication load, energy consumption, ...
133
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IPPS
2010
IEEE
15 years 1 months ago
2010
IEEE
It is possible to implement the parallel random access machine (PRAM) on a chip multiprocessor (CMP) efficiently with an emulated shared memory (ESM) architecture to gain easy par...