Sciweavers

73 search results - page 13 / 15
» Modeling Traceability of Concerns for Synchronizing Architec...
Sort
View
PODC
2009
ACM
15 years 8 months ago
Memory models: a case for rethinking parallel languages and hardware
The era of parallel computing for the masses is here, but writing correct parallel programs remains far more difficult than writing sequential programs. Aside from a few domains,...
Sarita V. Adve
AI
2008
Springer
14 years 11 months ago
The well-designed young mathematician
This paper complements McCarthy's "The well designed child", in part by putting it in a broader context, the space of possible well designed progeny, and in part by...
Aaron Sloman
CCECE
2006
IEEE
15 years 4 months ago
QOS Driven Network-on-Chip Design for Real Time Systems
Real Time embedded system designers are facing extreme challenges in underlying architectural design selection. It involves the selection of a programmable, concurrent, heterogene...
Ankur Agarwal, Mehmet Mustafa, Abhijit S. Pandya
DAC
1994
ACM
15 years 2 months ago
The Design of High-Performance Microprocessors at Digital
Today's high-performance single-chip CMOS microprocessors are the most complex and challenging chip designs ever implemented. To stay on the leading edge, Digital's micro...
Thomas F. Fox
98
Voted
PPOPP
2009
ACM
15 years 11 months ago
An efficient transactional memory algorithm for computing minimum spanning forest of sparse graphs
Due to power wall, memory wall, and ILP wall, we are facing the end of ever increasing single-threaded performance. For this reason, multicore and manycore processors are arising ...
Seunghwa Kang, David A. Bader