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IEEEPACT
2009
IEEE
15 years 2 months ago
FASTM: A Log-based Hardware Transactional Memory with Fast Abort Recovery
Abstract--Version management, one of the key design dimensions of Hardware Transactional Memory (HTM) systems, defines where and how transactional modifications are stored. Current...
Marc Lupon, Grigorios Magklis, Antonio Gonzá...
ET
2007
101views more  ET 2007»
15 years 5 months ago
Towards Nanoelectronics Processor Architectures
In this paper, we focus on reliability, one of the most fundamental and important challenges, in the nanoelectronics environment. For a processor architecture based on the unreliab...
Wenjing Rao, Alex Orailoglu, Ramesh Karri
CJ
2006
84views more  CJ 2006»
15 years 5 months ago
Instruction Level Parallelism through Microthreading - A Scalable Approach to Chip Multiprocessors
Most microprocessor chips today use an out-of-order instruction execution mechanism. This mechanism allows superscalar processors to extract reasonably high levels of instruction ...
Kostas Bousias, Nabil Hasasneh, Chris R. Jesshope
ASPLOS
2006
ACM
15 years 11 months ago
Unbounded page-based transactional memory
Exploiting thread level parallelism is paramount in the multi-core era. Transactions enable programmers to expose such parallelism by greatly simplifying the multi-threaded progra...
Weihaw Chuang, Satish Narayanasamy, Ganesh Venkate...
ICFCA
2004
Springer
15 years 10 months ago
FCA in Knowledge Technologies: Experiences and Opportunities
Abstract. Managing knowledge is a difficult and slippery enterprise. A wide variety of technologies have to be invoked in providing support for knowledge requirements, ranging fro...
Yannis Kalfoglou, Srinandan Dasmahapatra, Yun-Heh ...