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SEKE
2010
Springer
14 years 9 months ago
Specification patterns can be formal and still easy
Abstract--Property specification is still one of the most challenging tasks for transference of software verification technology like model checking. The use of patterns has been p...
Fernando Asteasuain, Víctor A. Braberman
POPL
2007
ACM
16 years 5 days ago
Proving that programs eventually do something good
In recent years we have seen great progress made in the area of automatic source-level static analysis tools. However, most of today's program verification tools are limited ...
Byron Cook, Alexey Gotsman, Andreas Podelski, Andr...
RTCSA
2003
IEEE
15 years 5 months ago
Introducing Temporal Analyzability Late in the Lifecycle of Complex Real-Time Systems
Many industrial real-time systems have evolved over a long period of time and were initially so simple that it was possible to predict consequences of adding new functionality by c...
Anders Wall, Johan Andersson, Jonas Neander, Chris...
WSC
2000
15 years 1 months ago
Use of discrete event simulation to validate an agent based scheduling engine
This paper discusses the use of simulation in a new context. Most often QUEST is viewed as a stand-alone simulation tool to analyze and understand shop floor behavior. It has rare...
Shubhabrata Biswas, Sara Merchawi
VLSID
2003
IEEE
180views VLSI» more  VLSID 2003»
16 years 6 days ago
Automating Formal Modular Verification of Asynchronous Real-Time Embedded Systems
Most verification tools and methodologies such as model checking, equivalence checking, hardware verification, software verification, and hardware-software coverification often fl...
Pao-Ann Hsiung, Shu-Yu Cheng