The analysis of CMOS VLSI circuit switching current has become an increasingly important and difficult task from both a VLSI design and simulation software perspective. This paper...
In this paper we propose a novel parameterized interconnect order reduction algorithm, CORE, to efficiently capture both inter-die and intra-die variations. CORE applies a two-ste...
Boolean satisfiability (SAT) based methods have traditionally been popular for formally verifying properties for digital circuits. We present a novel methodology for formulating a...
Saurabh K. Tiwary, Anubhav Gupta, Joel R. Phillips...
9, IO]. However, unlike the case with static timing, it is not so easy We show how recent advances in the handling of correlated interval representations of range uncertainty can b...
Process variations in nanometer technologies are becoming an important issue for cutting-edge FPGAs with a multimillion gate capacity. Considering both die-to-die and withindie va...