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ICCAD
1996
IEEE
151views Hardware» more  ICCAD 1996»
15 years 5 months ago
Expected current distributions for CMOS circuits
The analysis of CMOS VLSI circuit switching current has become an increasingly important and difficult task from both a VLSI design and simulation software perspective. This paper...
Dennis J. Ciplickas, Ronald A. Rohrer
ICCAD
2005
IEEE
101views Hardware» more  ICCAD 2005»
15 years 10 months ago
Parameterized interconnect order reduction with explicit-and-implicit multi-parameter moment matching for inter/intra-die variat
In this paper we propose a novel parameterized interconnect order reduction algorithm, CORE, to efficiently capture both inter-die and intra-die variations. CORE applies a two-ste...
Xin Li, Peng Li, Lawrence T. Pileggi
ICCAD
2009
IEEE
159views Hardware» more  ICCAD 2009»
14 years 11 months ago
First steps towards SAT-based formal analog verification
Boolean satisfiability (SAT) based methods have traditionally been popular for formally verifying properties for digital circuits. We present a novel methodology for formulating a...
Saurabh K. Tiwary, Anubhav Gupta, Joel R. Phillips...
ICCAD
2004
IEEE
147views Hardware» more  ICCAD 2004»
15 years 10 months ago
Interval-valued reduced order statistical interconnect modeling
9, IO]. However, unlike the case with static timing, it is not so easy We show how recent advances in the handling of correlated interval representations of range uncertainty can b...
James D. Ma, Rob A. Rutenbar
ICCAD
2005
IEEE
106views Hardware» more  ICCAD 2005»
15 years 10 months ago
FPGA device and architecture evaluation considering process variations
Process variations in nanometer technologies are becoming an important issue for cutting-edge FPGAs with a multimillion gate capacity. Considering both die-to-die and withindie va...
Ho-Yan Wong, Lerong Cheng, Yan Lin, Lei He