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ICCAD
2006
IEEE
141views Hardware» more  ICCAD 2006»
15 years 10 months ago
Design optimization for single-event upset robustness using simultaneous dual-VDD and sizing techniques
An optimization algorithm for the design of combinational circuits that are robust to single-event upsets (SEUs) is described. A simple, highly accurate model for the SEU robustne...
Mihir R. Choudhury, Quming Zhou, Kartik Mohanram
ICCAD
1996
IEEE
144views Hardware» more  ICCAD 1996»
15 years 5 months ago
Validation coverage analysis for complex digital designs
The functional validation of a state-of-the-art digital design is usually performed by simulation of a register-transfer-level model. The degree to which the testvector suite cove...
Richard C. Ho, Mark Horowitz
ICCAD
2004
IEEE
145views Hardware» more  ICCAD 2004»
15 years 10 months ago
Asymptotic probability extraction for non-normal distributions of circuit performance
While process variations are becoming more significant with each new IC technology generation, they are often modeled via linear regression models so that the resulting performanc...
Xin Li, Jiayong Le, Padmini Gopalakrishnan, Lawren...
ICCAD
2005
IEEE
147views Hardware» more  ICCAD 2005»
15 years 10 months ago
NoCEE: energy macro-model extraction methodology for network on chip routers
In this paper we present NoCEE, a fast and accurate method for extracting energy models for packet-switched Network on Chip (NoC) routers. Linear regression is used to model the r...
Jeremy Chan, Sri Parameswaran
ICCAD
2004
IEEE
80views Hardware» more  ICCAD 2004»
15 years 10 months ago
Techniques for improving the accuracy of geometric-programming based analog circuit design optimization
We present techniques for improving the accuracy of geometric-programming (GP) based analog circuit design optimization. We describe major sources of discrepancies between the res...
Jintae Kim, Jaeseo Lee, Lieven Vandenberghe