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ICCAD
2002
IEEE
92views Hardware» more  ICCAD 2002»
15 years 10 months ago
Optimization of a fully integrated low power CMOS GPS receiver
This paper describes an optimization technique able to optimize a complete wireless receiver architecture in a reasonable amount of time. The optimizer alternates between spice le...
Peter J. Vancorenland, Philippe Coppejans, Wouter ...
ICCAD
2008
IEEE
200views Hardware» more  ICCAD 2008»
14 years 7 months ago
Accurate Equivalent Energy Breakeven Time Estimation for Power Gating
Run-time Power Gating (RTPG) is a recent technique, which aims at aggressively reducing leakage power consumption. Energy breakeven time (EBT), or equivalent sleep time has been pr...
Hao Xu, Wen-Ben Jone, Ranga Vemuri
ICCAD
2006
IEEE
124views Hardware» more  ICCAD 2006»
15 years 10 months ago
Robust system level design with analog platforms
An approach to robust system level mixed signal design is presented based on analog platforms. The bottom-up characterization phase of platform components provides accurate perfor...
Fernando De Bernardinis, Pierluigi Nuzzo, Alberto ...
ICCAD
2003
IEEE
142views Hardware» more  ICCAD 2003»
15 years 10 months ago
SuPREME: Substrate and Power-delivery Reluctance-Enhanced Macromodel Evaluation
The recent demand for system-on-chip RF mixed-signal design and aggressive supply-voltage reduction require chip-level accurate analysis of both the substrate and power delivery s...
Tsung-Hao Chen, Clement Luk, Charlie Chung-Ping Ch...
ICCAD
1994
IEEE
121views Hardware» more  ICCAD 1994»
15 years 5 months ago
A cell-based power estimation in CMOS combinational circuits
In this paper we present a power dissipation model considering the charging/discharging of capacitance at the gate output node as well as internal nodes, and capacitance feedthrou...
Jiing-Yuan Lin, Tai-Chien Liu, Wen-Zen Shen