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ASPLOS
2010
ACM
15 years 10 months ago
Cortical architectures on a GPGPU
As the number of devices available per chip continues to increase, the computational potential of future computer architectures grows likewise. While this is a clear benefit for f...
Andrew Nere, Mikko Lipasti
LCN
2007
IEEE
15 years 10 months ago
Node Connectivity in Vehicular Ad Hoc Networks with Structured Mobility
1 Vehicular Ad hoc NETworks (VANETs) is a subclass of Mobile Ad hoc NETworks (MANETs). However, automotive ad hoc networks will behave in fundamentally different ways than the pred...
Ivan Wang Hei Ho, Kin K. Leung, John W. Polak, Rah...
BMCBI
2007
143views more  BMCBI 2007»
15 years 4 months ago
Factor analysis for gene regulatory networks and transcription factor activity profiles
Background: Most existing algorithms for the inference of the structure of gene regulatory networks from gene expression data assume that the activity levels of transcription fact...
Iosifina Pournara, Lorenz Wernisch
ICCAD
2007
IEEE
98views Hardware» more  ICCAD 2007»
16 years 29 days ago
Device-circuit co-optimization for mixed-mode circuit design via geometric programming
Modern processing technologies offer a number of types of devices such as high-VT , low-VT , thick-oxide, etc. in addition to the nominal transistor in order to meet system perfor...
Jintae Kim, Ritesh Jhaveri, Jason Woo, Chih-Kong K...
ICCAD
2006
IEEE
112views Hardware» more  ICCAD 2006»
16 years 29 days ago
A new RLC buffer insertion algorithm
Most existing buffering algorithms neglect the impact of inductance on circuit performance, which causes large error in circuit analysis and optimization. Even for the approaches...
Zhanyuan Jiang, Shiyan Hu, Jiang Hu, Zhuo Li, Weip...
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