Design debug remains one of the major bottlenecks in the VLSI design cycle today. Existing automated solutions strive to aid engineers in reducing the debug effort by identifying ...
Yibin Chen, Sean Safarpour, Andreas G. Veneris, Jo...
We present a CPU scheduling algorithm, called Energy-efficient Utility Accrual Algorithm (or EUA), for battery-powered, embedded real-time systems. We consider an embedded softwar...
Haisang Wu, Binoy Ravindran, E. Douglas Jensen, Pe...
Three-dimensional structure information can be estimated from two-dimensional images using recursive estimation methods. This paper investigates possibilities to improve structure...
Fredrik Nyberg, Ola Dahl, Jan Holst, Anders Heyden
Although recently there has been an increasing interest in studing genetically-based development using Artificial Life models, the mapping of the genetic information into the phen...
In this paper, a new approach to analog test design based on the circuit design process, called Characteristic Observation Inference (COI), is presented. In many situations, it is...
Walter M. Lindermeir, Helmut E. Graeb, Kurt Antrei...