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ISCA
2006
IEEE
130views Hardware» more  ISCA 2006»
15 years 3 months ago
Area-Performance Trade-offs in Tiled Dataflow Architectures
: Tiled architectures, such as RAW, SmartMemories, TRIPS, and WaveScalar, promise to address several issues facing conventional processors, including complexity, wire-delay, and pe...
Steven Swanson, Andrew Putnam, Martha Mercaldi, Ke...
ECSA
2010
Springer
15 years 5 months ago
Software Architecture Constraints as Customizable, Reusable and Composable Entities
One of the major advantages of component-based software engineering is the ability for developers to reuse and assemble software entities to build complex software. Whereas decompo...
Chouki Tibermacine, Christophe Dony, Salah Sadou, ...
IFIP
2009
Springer
15 years 1 months ago
Classifying Enterprise Architecture Analysis Approaches
Abstract. Enterprise architecture (EA) management forms a commonly accepted means to enhance the alignment of business and IT, and to support the managed evolution of the enterpris...
Sabine Buckl, Florian Matthes, Christian M. Schwed...
ASPLOS
2009
ACM
15 years 10 months ago
Architectural implications of nanoscale integrated sensing and computing
This paper explores the architectural implications of integrating computation and molecular probes to form nanoscale sensor processors (nSP). We show how nSPs may enable new compu...
Constantin Pistol, Christopher Dwyer, Alvin R. Leb...
DSD
2003
IEEE
138views Hardware» more  DSD 2003»
15 years 9 months ago
A Two-step Genetic Algorithm for Mapping Task Graphs to a Network on Chip Architecture
Network on Chip (NoC) is a new paradigm for designing core based System on Chip which supports high degree of reusability and is scalable. In this paper we describe an efficient t...
Tang Lei, Shashi Kumar