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ISCA
2000
IEEE
63views Hardware» more  ISCA 2000»
15 years 8 months ago
An embedded DRAM architecture for large-scale spatial-lattice computations
Spatial-lattice computations with finite-range interactions are an important class of easily parallelized computations. This class includes many simple and direct algorithms for ...
Norman Margolus
EUROPAR
2010
Springer
15 years 5 months ago
Thread Owned Block Cache: Managing Latency in Many-Core Architecture
Abstract. Shared last level cache is crucial to performance. However, multithread program model incurs serious contention in shared cache. In this paper, to reduce average cache ac...
Fenglong Song, Zhiyong Liu, Dongrui Fan, Hao Zhang...
JUCS
2000
120views more  JUCS 2000»
15 years 3 months ago
Execution and Cache Performance of the Scheduled Dataflow Architecture
: This paper presents an evaluation of our Scheduled Dataflow (SDF) Processor. Recent focus in the field of new processor architectures is mainly on VLIW (e.g. IA-64), superscalar ...
Krishna M. Kavi, Joseph Arul, Roberto Giorgi
UML
2005
Springer
15 years 9 months ago
Modeling Crosscutting Services with UML Sequence Diagrams
Abstract. Current software systems increasingly consist of distributed interacting components. The use of web services and similar middleware technologies strongly fosters such arc...
Martin Deubler, Michael Meisinger, Sabine Rittmann...
152
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ISMIR
2005
Springer
176views Music» more  ISMIR 2005»
15 years 9 months ago
On the Modeling of Time Information for Automatic Genre Recognition Systems in Audio Signals
The creation of huge databases coming from both restoration of existing analogue archives and new content is demanding fast and more and more reliable tools for content analysis a...
Nicolas Scaringella, Giorgio Zoia