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CASES
2001
ACM
15 years 8 months ago
A system-on-a-chip lock cache with task preemption support
Intertask/interprocess synchronization overheads may be significant in a multiprocessor-shared memory System-on-a-Chip implementation. These overheads are observed in terms of loc...
Bilge Saglam Akgul, Jaehwan Lee, Vincent John Moon...
AAAI
2006
15 years 6 months ago
AWDRAT: A Cognitive Middleware System for Information Survivability
The Infrastructure of modern society is controlled by software systems that are vulnerable to attacks. Many such attacks, launched by "recreational hackers" have already...
Howard E. Shrobe, Robert Laddaga, Robert Balzer, N...
DBSEC
2004
170views Database» more  DBSEC 2004»
15 years 6 months ago
RBAC/MAC Security Analysis and Design for UML
In software construction, analysis investigates the boundary of a system (scope and requirements), its usage and access, and from a security perspective, who needs access to what ...
Thuong Doan, Steven A. Demurjian, Charles E. Phill...
140
Voted
BMCBI
2004
98views more  BMCBI 2004»
15 years 4 months ago
Incidence of "quasi-ditags" in catalogs generated by Serial Analysis of Gene Expression (SAGE)
Background: Serial Analysis of Gene Expression (SAGE) is a functional genomic technique that quantitatively analyzes the cellular transcriptome. The analysis of SAGE libraries rel...
Sergey V. Anisimov, Alexei A. Sharov
MICRO
2010
IEEE
156views Hardware» more  MICRO 2010»
15 years 3 months ago
Explicit Communication and Synchronization in SARC
SARC merges cache controller and network interface functions by relying on a single hardware primitive: each access checks the tag and the state of the addressed line for possible...
Manolis Katevenis, Vassilis Papaefstathiou, Stamat...
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