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ASPDAC
2004
ACM
107views Hardware» more  ASPDAC 2004»
13 years 12 months ago
Interconnect capacitance estimation for FPGAs
Abstract—The dynamic power consumed by a digital CMOS circuit is directly proportional to capacitance. In this paper, we consider pre-routing capacitance estimation for FPGAs and...
Jason Helge Anderson, Farid N. Najm
FCCM
2006
IEEE
162views VLSI» more  FCCM 2006»
14 years 15 days ago
Power Visualization, Analysis, and Optimization Tools for FPGAs
This paper introduces the Low-Power Intelligent Tool Environment (LITE), an object oriented tool set designed for power visualization, analysis, and optimization. These tools lever...
Matthew French, Li Wang, Michael J. Wirthlin
GECCO
2008
Springer
146views Optimization» more  GECCO 2008»
13 years 7 months ago
A formal performance modeling framework for bio-inspired ad hoc routing protocols
Bio-inspired ad hoc routing is an active area of research. The designers of these algorithms predominantly evaluate the performance of their protocols with the help of simulation ...
Muhammad Saleem, Syed Ali Khayam, Muddassar Farooq
FPGA
2004
ACM
163views FPGA» more  FPGA 2004»
13 years 10 months ago
Time and area efficient pattern matching on FPGAs
Pattern matching for network security and intrusion detection demands exceptionally high performance. Much work has been done in this field, and yet there is still significant roo...
Zachary K. Baker, Viktor K. Prasanna
GLOBECOM
2010
IEEE
13 years 3 months ago
Circulant-Graph-Based Fault-Tolerant Routing for All-Optical WDM LANs
High demands in data delivery latency and communication reliability encourage the use of fault-toleranceenhanced all-optical WDM networks. Low latency is satisfied by setting up a ...
Dexiang Wang, Janise McNair