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» Modeling the variability of architectural patterns
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HPCA
2009
IEEE
16 years 4 months ago
Optimizing communication and capacity in a 3D stacked reconfigurable cache hierarchy
Cache hierarchies in future many-core processors are expected to grow in size and contribute a large fraction of overall processor power and performance. In this paper, we postula...
Niti Madan, Li Zhao, Naveen Muralimanohar, Anirudd...
GECCO
2007
Springer
300views Optimization» more  GECCO 2007»
15 years 10 months ago
A NSGA-II, web-enabled, parallel optimization framework for NLP and MINLP
Engineering design increasingly uses computer simulation models coupled with optimization algorithms to find the best design that meets the customer constraints within a time con...
David J. Powell, Joel K. Hollingsworth
ICARCV
2006
IEEE
420views Robotics» more  ICARCV 2006»
15 years 10 months ago
Recognizing People's Faces: from Human to Machine Vision
— As confirmed by recent neurophysiological studies, the use of dynamic information is extremely important for humans in visual perception of biological forms and motion. Apart ...
Massimo Tistarelli, Manuele Bicego, Enrico Grosso
ISVLSI
2005
IEEE
101views VLSI» more  ISVLSI 2005»
15 years 10 months ago
eWatch: Context Sensitive System Design Case Study
In this paper, we introduce a novel context sensitive system design paradigm. Multiple sensors/ computational architecture, in the form of our eWatch device, is used to infer the ...
Asim Smailagic, Daniel P. Siewiorek, Uwe Maurer, A...
ASPDAC
2000
ACM
104views Hardware» more  ASPDAC 2000»
15 years 8 months ago
Design of digital neural cell scheduler for intelligent IB-ATM switch
— We present the architecture of the ATM banyan switch composed of pattern process and high-speed digital neural cell scheduler. An input buffer type ATM switch with a window-bas...
J.-K. Lee, Seung-Min Lee, Mike Myung-Ok Lee, D.-W....