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» Modelling Immunological Memory
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158
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ISPASS
2010
IEEE
15 years 5 months ago
Understanding transactional memory performance
Abstract—Transactional memory promises to generalize transactional programming to mainstream languages and data structures. The purported benefit of transactions is that they ar...
Donald E. Porter, Emmett Witchel
HPCA
2005
IEEE
16 years 3 months ago
Using Virtual Load/Store Queues (VLSQs) to Reduce the Negative Effects of Reordered Memory Instructions
The use of large instruction windows coupled with aggressive out-oforder and prefetching capabilities has provided significant improvements in processor performance. In this paper...
Aamer Jaleel, Bruce L. Jacob
ARCS
2009
Springer
15 years 10 months ago
Improving Memory Subsystem Performance Using ViVA: Virtual Vector Architecture
The disparity between microprocessor clock frequencies and memory latency is a primary reason why many demanding applications run well below peak achievable performance. Software c...
Joseph Gebis, Leonid Oliker, John Shalf, Samuel Wi...
124
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DSN
2007
IEEE
15 years 9 months ago
Electing an Eventual Leader in an Asynchronous Shared Memory System
This paper considers the problem of electing an eventual leader in an asynchronous shared memory system. While this problem has received a lot of attention in messagepassing syste...
Antonio Fernández, Ernesto Jiménez, ...
164
Voted
SIGSOFT
2006
ACM
15 years 9 months ago
Memories of bug fixes
The change history of a software project contains a rich collection of code changes that record previous development experience. Changes that fix bugs are especially interesting, ...
Sunghun Kim, Kai Pan, E. James Whitehead Jr.