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» Modelling Immunological Memory
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138
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MICRO
2010
IEEE
202views Hardware» more  MICRO 2010»
14 years 10 months ago
Hardware Support for Relaxed Concurrency Control in Transactional Memory
Today's transactional memory systems implement the two-phase-locking (2PL) algorithm which aborts transactions every time a conflict happens. 2PL is a simple algorithm that pr...
Utku Aydonat, Tarek S. Abdelrahman
EUROPAR
1999
Springer
15 years 7 months ago
DAOS - Scalable And-Or Parallelism
Abstract. This paper presents DAOS, a model for exploitation of Andand Or-parallelism in logic programs. DAOS assumes a physically distributed memory environment and a logically sh...
Luís Fernando Castro, Vítor Santos C...
ICS
2009
Tsinghua U.
15 years 10 months ago
QuakeTM: parallelizing a complex sequential application using transactional memory
“Is transactional memory useful?” is the question that cannot be answered until we provide substantial applications that can evaluate its capabilities. While existing TM appli...
Vladimir Gajinov, Ferad Zyulkyarov, Osman S. Unsal...
112
Voted
MICRO
2009
IEEE
132views Hardware» more  MICRO 2009»
15 years 10 months ago
EazyHTM: eager-lazy hardware transactional memory
Transactional Memory aims to provide a programming model that makes parallel programming easier. Hardware implementations of transactional memory (HTM) suffer from fewer overhead...
Sasa Tomic, Cristian Perfumo, Chinmay Eishan Kulka...
NOCS
2008
IEEE
15 years 10 months ago
Debugging Distributed-Shared-Memory Communication at Multiple Granularities in Networks on Chip
We present a methodology to debug a SOC by concentrating on its communication. Our extended communication model includes a) multiple signal groups per interface protocol at each I...
Bart Vermeulen, Kees Goossens, Siddharth Umrani