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ICCD
2004
IEEE
129views Hardware» more  ICCD 2004»
16 years 16 days ago
Cache Array Architecture Optimization at Deep Submicron Technologies
A cache access time model, PRACTICS (PRedictor of Access and Cycle TIme for Cache Stack), has been developed to optimize the memory array architecture for the minimum access and c...
Annie (Yujuan) Zeng, Kenneth Rose, Ronald J. Gutma...
98
Voted
WSC
2001
15 years 5 months ago
A simulation study of the labor and delivery rooms at JMH
This paper presents a simulation model of the operations in the Labor and Delivery Rooms at Jackson Memorial Hospital. A thorough analysis of the contents of hospital's datab...
Martha A. Centeno, Marsha A. Lee, Elizabeth Lopez,...
IANDC
2011
84views more  IANDC 2011»
14 years 10 months ago
Teaching randomized learners with feedback
The present paper introduces a new model for teaching randomized learners. Our new model, though based on the classical teaching dimension model, allows to study the influence of...
Frank J. Balbach, Thomas Zeugmann
124
Voted
ICSM
2009
IEEE
15 years 10 months ago
Visualizing the Java heap demonstration proposal
Many of the problems that occur in long-running systems involve the way that the system uses memory. We have developed a framework for extracting and building a model of the heap ...
Steven P. Reiss
124
Voted
ADBIS
2007
Springer
110views Database» more  ADBIS 2007»
15 years 9 months ago
Design of Web Agents Inspired by Brain Research
The paper presents an approach to combine knowledge from memory and brain sciences with information retrieval research in the design of Web agents. An information retrieval agent f...
Maya Dimitrova, Hiroaki Wagatsuma, Yoko Yamaguchi