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HPCA
1999
IEEE
15 years 2 months ago
Improving the Accuracy vs. Speed Tradeoff for Simulating Shared-Memory Multiprocessors with ILP Processors
Previous simulators for shared-memory architectures have imposed a large tradeoff between simulation accuracy and speed. Most such simulators model simple processors that do not e...
Murthy Durbhakula, Vijay S. Pai, Sarita V. Adve
SAB
2010
Springer
150views Optimization» more  SAB 2010»
14 years 7 months ago
Internal Models in the Cerebellum: A Coupling Scheme for Online and Offline Learning in Procedural Tasks
The cerebellum plays a major role in motor control. It is thought to mediate the acquisition of forward and inverse internal models of the bodyenvironment interaction [1]. In this ...
Jean-Baptiste Passot, Niceto Luque, Angelo Arleo
IJFCS
2010
92views more  IJFCS 2010»
14 years 7 months ago
Collapsing the Hierarchy of Parallel Computational Models
We investigate the computational power of parallel models with directed reconfigurable buses and with shared memory. Based on feasibility considerations present in the literature,...
Stefan D. Bruda, Yuanqiao Zhang
CVPR
2011
IEEE
14 years 7 months ago
Distributed Message Passing for Large Scale Graphical Models
In this paper we propose a distributed message-passing algorithm for inference in large scale graphical models. Our method can handle large problems efficiently by distributing a...
Alexander Schwing, Hazan Tamir, Marc Pollefeys, Ra...
CADE
2012
Springer
13 years 11 days ago
EPR-Based Bounded Model Checking at Word Level
We propose a word level, bounded model checking (BMC) algorithm based on translation into the effectively propositional fragment (EPR) of firstorder logic. This approach to BMC al...
Moshe Emmer, Zurab Khasidashvili, Konstantin Korov...