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ICCD
2007
IEEE
225views Hardware» more  ICCD 2007»
16 years 3 months ago
Fine grain 3D integration for microarchitecture design through cube packing exploration
Most previous 3D IC research focused on “stacking” traditional 2D silicon layers, so the interconnect reduction is limited to interblock delays. In this paper, we propose tech...
Yongxiang Liu, Yuchun Ma, Eren Kursun, Glenn Reinm...
ICCD
2005
IEEE
101views Hardware» more  ICCD 2005»
16 years 3 months ago
Three-Dimensional Cache Design Exploration Using 3DCacti
As technology scales, interconnects dominate the performance and power behavior of deep submicron designs. Three-dimensional integrated circuits (3D ICs) have been proposed as a w...
Yuh-Fang Tsai, Yuan Xie, Narayanan Vijaykrishnan, ...
ICCD
2005
IEEE
102views Hardware» more  ICCD 2005»
16 years 3 months ago
Monitoring Temperature in FPGA based SoCs
FPGA logic densities continue to increase at a tremendous rate. This has had the undesired consequence of increased power density, which manifests itself as higher ondie temperatu...
Sivakumar Velusamy, Wei Huang, John Lach, Mircea R...
CVPR
2010
IEEE
16 years 2 months ago
Learning Mid-Level Features For Recognition
Many successful models for scene or object recognition transform low-level descriptors (such as Gabor filter responses, or SIFT descriptors) into richer representations of interme...
Y-Lan Boureau, Francis Bach, Yann LeCun, Jean Ponc...
WWW
2010
ACM
16 years 1 months ago
Automated performance assessment for service-oriented middleware: a case study on BPEL engines
Middleware for Web service compositions, such as BPEL engines, provides the execution environment for services as well as additional functionalities, such as monitoring and self-t...
Domenico Bianculli, Walter Binder, Mauro Luigi Dra...
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