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CAV
2010
Springer
282views Hardware» more  CAV 2010»
15 years 8 months ago
A NuSMV Extension for Graded-CTL Model Checking
Graded-CTL is an extension of CTL with graded quantifiers which allow to reason about either at least or all but any number of possible futures. In this paper we show an extension...
Alessandro Ferrante, Maurizio Memoli, Margherita N...
TACAS
1998
Springer
81views Algorithms» more  TACAS 1998»
15 years 8 months ago
Formal Design and Analysis of a Gear Controller
In this paper, we report on an application of the validation and veri cation tool kit Uppaal in the design and analysis of a prototype gear controller, carried out in a joint proje...
Magnus Lindahl, Paul Pettersson, Wang Yi
QEST
2005
IEEE
15 years 10 months ago
iLTLChecker: A Probabilistic Model Checker for Multiple DTMCs
iLTL is a probabilistic temporal logic that can specify properties of multiple discrete time Markov chains (DTMCs). In this paper, we describe two related tools: MarkovEstimator a...
YoungMin Kwon, Gul A. Agha
GG
2010
Springer
15 years 5 months ago
Local Confluence for Rules with Nested Application Conditions
Abstract. Local confluence is an important property in many rewriting and transformation systems. The notion of critical pairs is central for being able to verify local confluence ...
Hartmut Ehrig, Annegret Habel, Leen Lambers, Ferna...
FPGA
2003
ACM
161views FPGA» more  FPGA 2003»
15 years 9 months ago
Implementation of BEE: a real-time large-scale hardware emulation engine
This paper describes the hardware implementation of a real-time, large-scale, multi-chip FPGA (Field Programmable Gate Array) based emulation engine with a capacity of 10 million ...
Chen Chang, Kimmo Kuusilinna, Brian C. Richards, R...