We present a mathematical model for the problem of scheduling tests for core-based system-on-chip (SOC) VLSI designs. Given a set of tests for each core in the SOC and a set of te...
— We develop a joint playout buffer and Forward Error Correction (FEC) adjustment scheme for Internet Telephony, which incorporates the impact of end-to-end delay on the perceive...
This paper addresses the issue of provisioning end-to-end bandwidth guarantees across multiple Autonomous Systems (ASes). We first review a cascaded model for negotiating and est...
Kin-Hon Ho, Michael P. Howarth, Ning Wang, George ...
Features representing information about pressure distribution from a static image of a handwritten signature are analyzed for an offline verification system. From gray-scale image...
Jesus Francisco Vargas Bonilla, Miguel Angel Ferre...
Instruction set simulators are critical tools for the exploration and validation of new programmable architectures. Due to increasing complexity of the architectures and timeto-ma...