Sciweavers

62 search results - page 8 / 13
» Modelling the ARMv8 architecture, operationally: concurrency...
Sort
View
POPL
2010
ACM
15 years 7 months ago
On the Verification Problem for Weak Memory Models
We address the verification problem of finite-state concurrent programs running under weak memory models. These models capture the reordering of program (read and write) operation...
Ahmed Bouajjani, Madanlal Musuvathi, Mohamed Faouz...
JCS
1998
117views more  JCS 1998»
14 years 9 months ago
A Semantic-Based Transaction Processing Model for Multilevel Transactions
Multilevel transactions have been proposed for multilevel secure databases; in contrast to most proposals, such transactions allow users to read and write across multiple security...
Indrakshi Ray, Paul Ammann, Sushil Jajodia
140
Voted
FPGA
2006
ACM
224views FPGA» more  FPGA 2006»
15 years 1 months ago
Flexible implementation of genetic algorithms on FPGAs
In this paper, we propose a technique to flexibly implement genetic algorithms for various problems on FPGAs. For the purpose, we propose a basic architecture for GA which consist...
Tatsuhiro Tachibana, Yoshihiro Murata, Naoki Shiba...
FPL
2001
Springer
123views Hardware» more  FPL 2001»
15 years 2 months ago
Compilation Increasing the Scheduling Scope for Multi-memory-FPGA-Based Custom Computing Machines
This paper presents new achievements on the automatic mapping of algorithms, written in imperative software programming languages, to custom computing machines. The reconfigurable ...
João M. P. Cardoso, Horácio C. Neto
FAST
2008
14 years 11 months ago
Enhancing Storage System Availability on Multi-Core Architectures with Recovery-Conscious Scheduling
In this paper we develop a recovery conscious framework for multi-core architectures and a suite of techniques for improving the resiliency and recovery efficiency of highly conc...
Sangeetha Seshadri, Lawrence Chiu, Cornel Constant...