6229 search results - page 14 / 1246 » Models of Computation for Networks on Chip |
IEEEPACT
2005
IEEE
15 years 3 months ago
2005
IEEE
While general-purpose processors have only recently employed chip multiprocessor (CMP) architectures, network processors (NPs) have used heterogeneous multi-core architectures sin...
52
Voted
NOCS
2009
IEEE
15 years 4 months ago
2009
IEEE
DAC
2001
ACM
15 years 10 months ago
2001
ACM
Using on-chip interconnection networks in place of ad-hoc global wiring structures the top level wires on a chip and facilitates modular design. With this approach, system modules...
DAC
2001
ACM
15 years 10 months ago
2001
ACM
ISCA
2000
IEEE
15 years 1 months ago
2000
IEEE
Spatial-lattice computations with finite-range interactions are an important class of easily parallelized computations. This class includes many simple and direct algorithms for ...