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» Models of Computation for Networks on Chip
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81
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NOCS
2007
IEEE
15 years 3 months ago
On the Design of a Photonic Network-on-Chip
Recent remarkable advances in nanoscale siliconphotonic integrated circuitry specifically compatible with CMOS fabrication have generated new opportunities for leveraging the uni...
Assaf Shacham, Keren Bergman, Luca P. Carloni
95
Voted
NOCS
2008
IEEE
15 years 3 months ago
Reducing the Interconnection Network Cost of Chip Multiprocessors
This paper introduces a cost-effective technique to deal with CMP coherence protocol requirements from the interconnection network point of view. A mechanism is presented to avoid...
Pablo Abad, Valentin Puente, José-Án...
ICPP
2005
IEEE
15 years 3 months ago
Peak Power Control for a QoS Capable On-Chip Network
In recent years integrating multiprocessors in a single chip is emerging for supporting various scientific and commercial applications, with diverse demands to the underlying on-c...
Yuho Jin, Eun Jung Kim, Ki Hwan Yum
100
Voted
AINA
2009
IEEE
15 years 2 months ago
Differences and Commonalities of Service-Oriented Device Architectures, Wireless Sensor Networks and Networks-on-Chip
Device centric Service-oriented Architectures have shown to be applicable in the automation industry for interconnecting manufacturing devices and enterprise systems, thus, establ...
Guido Moritz, Claas Cornelius, Frank Golatowski, D...
84
Voted
IPPS
2003
IEEE
15 years 2 months ago
SoCBUS: Switched Network on Chip for Hard Real Time Embedded Systems
With the current trend in integration of more complex systems on chip there is a need for better communication infrastructure on chip that will increase the available bandwidth an...
Daniel Wiklund, Dake Liu