6229 search results - page 81 / 1246 » Models of Computation for Networks on Chip |
200
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ERSA
2010
15 years 4 months ago
2010
Interconnect architecture is a primary research issue for emerging many-core processors. Packet switched Networks-on-Chip (NoCs) are considered key to success but since they delive...
164
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PDPTA
1996
15 years 7 months ago
1996
This paper describes a parallelization of the sequential dynamic programming method for solving a 2D knapsack problem where multiples of n rectangular objects are optimally packed...
181
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DAC
1997
ACM
15 years 9 months ago
1997
ACM
We present our experiences with the formal verification of an automotive chip used to control the safety features in a car. We used a BDD based model checker in our work. We descr...
175
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BMCBI
2006
15 years 6 months ago
2006
Background: The identification of differentially expressed genes (DEGs) from Affymetrix GeneChips arrays is currently done by first computing expression levels from the low-level ...