10 search results - page 1 / 2 » Modular Synthesis of Timed Circuits using Partial Order Redu... |
66
Voted
ENTCS
2002
14 years 9 months ago
2002
ICCD
1999
IEEE
15 years 1 months ago
1999
IEEE
ions", in IEEE Transactions on CAD of VLSI, 25(3):403-412, March, 2006. , E. Mercer, C. Myers, "Modular Verification of Timed Systems Using Automatic Abstraction" in...
ASYNC
1997
IEEE
15 years 1 months ago
1997
IEEE
This paper presents new timing analysis algorithms for efficient state space exploration during timed circuit synthesis. Timed circuits are a class of asynchronous circuits that i...
ICCAD
2006
IEEE
15 years 3 months ago
2006
IEEE
Designing asynchronous circuits by reusing existing synchronous tools has become a promising solution to the problem of poor CAD support in asynchronous world. A straightforward w...
DAC
2004
ACM
15 years 10 months ago
2004
ACM
Logic duplication, a commonly used synthesis technique to remove trapped inverters in reconvergent paths of Domino circuits, incurs high area and power penalties. In this paper, w...