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EDCC
2008
Springer
15 years 2 months ago
A Transient-Resilient System-on-a-Chip Architecture with Support for On-Chip and Off-Chip TMR
The ongoing technological advances in the semiconductor industry make Multi-Processor System-on-a-Chips (MPSoCs) more attractive, because uniprocessor solutions do not scale satis...
Roman Obermaisser, Hubert Kraut, Christian El Sall...
SPRINGSIM
2007
15 years 1 months ago
An architecture for wireless simulation in NS-2 applied to impulse-radio ultra-wide band networks
We present an architecture for implementing a wireless physical layer in a packet-based network simulator. We integrate this architecture in the popular ns-2 network simulator and...
Ruben Merz, Jean-Yves Le Boudec, Jörg Widmer
104
Voted
ISCA
2000
IEEE
103views Hardware» more  ISCA 2000»
15 years 4 months ago
Piranha: a scalable architecture based on single-chip multiprocessing
The microprocessor industry is currently struggling with higher development costs and longer design times that arise from exceedingly complex processors that are pushing the limit...
Luiz André Barroso, Kourosh Gharachorloo, R...
101
Voted
AIPS
1994
15 years 1 months ago
Testing Incremental Adaptation
A robot system operating in an environmentin which there is uncertainty and changeneeds to combinethe ability to react withthe ability to plan ahead. In a previous paper wepropose...
Damian M. Lyons, Antonius J. Hendriks
JFR
2006
108views more  JFR 2006»
15 years 14 days ago
Learning in a hierarchical control system: 4D/RCS in the DARPA LAGR program
The Defense Applied Research Projects Agency (DARPA) Learning Applied to Ground Vehicles (LAGR) program aims to develop algorithms for autonomous vehicle navigation that learn how...
James S. Albus, Roger Bostelman, Tommy Chang, Tsai...