14 search results - page 2 / 3 » Modulo scheduling for a fully-distributed clustered VLIW arc... |
55
Voted
SPE
2008
14 years 11 months ago
2008
103
click to vote
CF
2004
ACM
15 years 5 months ago
2004
ACM
Centralized register file architectures scale poorly in terms of clock rate, chip area, and power consumption and are thus not suitable for consumer electronic devices. The conse...
IEEEPACT
2000
IEEE
15 years 4 months ago
2000
IEEE
Recent digital signal processors (DSPs) show a homogeneous VLIW-like data path architecture, which allows C compilers to generate efficient code. However, still some special rest...
89
Voted
DAC
2002
ACM
16 years 18 days ago
2002
ACM
Aim of this paper is to propose a methodology for the definition of an instruction-level energy estimation framework for VLIW (Very Long Instruction Word) processors. The power mo...
86
Voted
CASES
2001
ACM
15 years 3 months ago
2001
ACM
In this paper we describe a design exploration methodology for clustered VLIW architectures. The central idea of this work is a set of three techniques aimed at reducing the cost ...