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DATE
2008
IEEE
204views Hardware» more  DATE 2008»
15 years 7 months ago
Deep Submicron Interconnect Timing Model with Quadratic Random Variable Analysis
Shrinking feature sizes and process variations are of increasing concern in modern technology. It is urgent that we develop statistical interconnect timing models which are harmon...
Jun-Kuei Zeng, Chung-Ping Chen
ATAL
2009
Springer
15 years 7 months ago
Towards multi-level modeling of self-assembling intelligent micro-systems
We investigate and model the dynamics of two-dimensional stochastic self-assembly of intelligent micro-systems with minimal requirements in terms of sensing, actuation, and contro...
Grégory Mermoud, Juergen Brugger, Alcherio ...
109
Voted
CF
2005
ACM
15 years 2 months ago
Grid result checking
Result checking is the theory and practice of proving that the result of an execution of a program on an input is correct. Result checking has most often been envisioned in the fr...
Cécile Germain-Renaud, Dephine Monnier-Raga...
127
Voted
TVLSI
2008
150views more  TVLSI 2008»
15 years 6 days ago
Data Memory Subsystem Resilient to Process Variations
As technology scales, more sophisticated fabrication processes cause variations in many different parameters in the device. These variations could severely affect the performance o...
M. Bennaser, Yao Guo, Csaba Andras Moritz
98
Voted
IPPS
2010
IEEE
14 years 10 months ago
On the parallelisation of MCMC by speculative chain execution
Abstract--The increasing availability of multi-core and multiprocessor architectures provides new opportunities for improving the performance of many computer simulations. Markov C...
Jonathan M. R. Byrd, Stephen A. Jarvis, Abhir H. B...