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VLSID
2002
IEEE
132views VLSI» more  VLSID 2002»
16 years 6 months ago
VLSI Architecture for a Flexible Motion Estimation with Parameters
If motion estimation can choose the most suitable algorithm according to the changing characteristics of input image signals, we can get benefits, which improve quality and perfor...
Jinku Choi, Nozomu Togawa, Masao Yanagisawa, Tatsu...
ISPASS
2010
IEEE
16 years 14 days ago
Hardware prediction of OS run-length for fine-grained resource customization
—In the past ten years, computer architecture has seen a paradigm shift from emphasizing single thread performance to energy efficient, throughput oriented, chip multiprocessors...
David Nellans, Kshitij Sudan, Rajeev Balasubramoni...
SIGCOMM
2009
ACM
16 years 3 days ago
ROAR: increasing the flexibility and performance of distributed search
To search the web quickly, search engines partition the web index over many machines, and consult every partition when answering a query. To increase throughput, replicas are adde...
Costin Raiciu, Felipe Huici, Mark Handley, David S...
GLOBECOM
2008
IEEE
16 years 2 days ago
Near-Capacity Three-Stage Downlink Iteratively Decoded Generalized Layered Space-Time Coding with Low Complexity
Abstract— This paper presents a low complexity iteratively detected space-time transmission architecture based on Generalized Layered Space-Time (GLST) codes and IRregular Convol...
Lingkun Kong, Soon Xin Ng, Lajos Hanzo
DATE
2006
IEEE
100views Hardware» more  DATE 2006»
15 years 11 months ago
Simulation and analysis of network on chip architectures: ring, spidergon and 2D mesh
NoC architectures can be adopted to support general communications among multiple IPs over multi-processor Systems on Chip (SoCs). In this work we illustrate the modeling and simu...
Luciano Bononi, Nicola Concer