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ISCA
1999
IEEE
105views Hardware» more  ISCA 1999»
15 years 7 months ago
The Program Decision Logic Approach to Predicated Execution
Modern compilers must expose sufficient amounts of Instruction-Level Parallelism (ILP) to achieve the promised performance increases of superscalar and VLIW processors. One of the...
David I. August, John W. Sias, Jean-Michel Puiatti...
127
Voted
FPL
2007
Springer
146views Hardware» more  FPL 2007»
15 years 9 months ago
Efficient External Memory Interface for Multi-processor Platforms Realized on FPGA Chips
The complexity of today’s embedded applications requires modern high-performance embedded System-on-Chip (SoC) platforms to be multiprocessor architectures. Advances in FPGA tec...
Hristo Nikolov, Todor Stefanov, Ed F. Deprettere
SAC
2010
ACM
15 years 3 months ago
Improving the efficiency of dynamic malware analysis
Each day, security companies see themselves confronted with thousands of new malware programs. To cope with these large quantities, researchers and practitioners alike have develo...
Ulrich Bayer, Engin Kirda, Christopher Kruegel
JCB
2006
140views more  JCB 2006»
15 years 3 months ago
HAPLOFREQ-Estimating Haplotype Frequencies Efficiently
A commonly used tool in disease association studies is the search for discrepancies between the haplotype distribution in the case and control populations. In order to find this d...
Eran Halperin, Elad Hazan
RTSS
1996
IEEE
15 years 7 months ago
Reducing the number of clock variables of timed automata
We propose a method for reducing the number of clocks of a timed automaton by combining two algorithms. The first one consists in detecting active clocks, that is, those clocks wh...
Conrado Daws, Sergio Yovine