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ISPD
2003
ACM
79views Hardware» more  ISPD 2003»
15 years 2 months ago
Floorplanning of pipelined array modules using sequence pairs
Floorplanning individual pipelined array modules of a larger overall die can yield beneficial results. Critical paths in every pipeline stage of a pipelined design are roughly equ...
Matthew Moe, Herman Schmit
HUC
2003
Springer
15 years 2 months ago
Finding a Place for UbiComp in the Home
The movement of design out of the workplace and into the home brings with it the need to develop new analytic concepts to consider how ubiquitous computing might relate to and supp...
Andy Crabtree, Tom Rodden, Terry Hemmings, Steve B...
GLVLSI
2010
IEEE
164views VLSI» more  GLVLSI 2010»
15 years 2 months ago
Performance and energy trade-offs analysis of L2 on-chip cache architectures for embedded MPSoCs
On-chip memory organization is one of the most important aspects that can influence the overall system behavior in multiprocessor systems. Following the trend set by high-perform...
Mohamed M. Sabry, Martino Ruggiero, Pablo Garcia D...
PLDI
2010
ACM
15 years 2 months ago
Mint: Java multi-stage programming using weak separability
Multi-stage programming (MSP) provides a disciplined approach to run-time code generation. In the purely functional setting, it has been shown how MSP can be used to reduce the ov...
Edwin Westbrook, Mathias Ricken, Jun Inoue, Yilong...
EVOW
2001
Springer
15 years 2 months ago
ARPIA: A High-Level Evolutionary Test Signal Generator
The integrated circuits design flow is rapidly moving towards higher description levels. However, test-related activities are lacking behind this trend, mainly since effective faul...
Fulvio Corno, Gianluca Cumani, Matteo Sonza Reorda...