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» Multi-Million Gate FPGA Physical Design Challenges
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ISLPED
2006
ACM
119views Hardware» more  ISLPED 2006»
15 years 3 months ago
Process variation aware cache leakage management
In a few technology generations, limitations of fabrication processes will make accurate design time power estimates a daunting challenge. Static leakage current which comprises a...
Ke Meng, Russ Joseph
88
Voted
ICASSP
2008
IEEE
15 years 4 months ago
Parameterized design framework for hardware implementation of particle filters
Particle filtering methods provide powerful techniques for solving non-linear state-estimation problems, and are applied to a variety of application areas in signal processing. Be...
Sankalita Saha, Neal K. Bambha, Shuvra S. Bhattach...
CODES
2008
IEEE
15 years 4 months ago
Don't forget memories: a case study redesigning a pattern counting ASIC circuit for FPGAs
Modern embedded compute platforms increasingly contain both microprocessors and field-programmable gate arrays (FPGAs). The FPGAs may implement accelerators or other circuits to s...
David Sheldon, Frank Vahid
CODES
2009
IEEE
15 years 1 months ago
Minimization of the reconfiguration latency for the mapping of applications on FPGA-based systems
Field-Programmable Gate Arrays (FPGAs) have become promising mapping fabric for the implementation of System-on-Chip (SoC) platforms, due to their large capacity and their enhance...
Vincenzo Rana, Srinivasan Murali, David Atienza, M...
NIXDORF
1992
116views Hardware» more  NIXDORF 1992»
15 years 1 months ago
Programmable Active Memories: A Performance Assessment
We present some quantitative performance measurements for the computing power of Programmable Active Memories (PAM), as introduced by [2]. Based on Field Programmable Gate Array (...
Patrice Bertin, Didier Roncin, Jean Vuillemin