Sciweavers

10 search results - page 2 / 2
» Multi-Robot Area Patrol under Frequency Constraints
Sort
View
DATE
2005
IEEE
143views Hardware» more  DATE 2005»
13 years 8 months ago
Statistical Modeling of Pipeline Delay and Design of Pipeline under Process Variation to Enhance Yield in sub-100nm Technologies
Operating frequency of a pipelined circuit is determined by the delay of the slowest pipeline stage. However, under statistical delay variation in sub-100nm technology regime, the...
Animesh Datta, Swarup Bhunia, Saibal Mukhopadhyay,...
HPCA
2006
IEEE
14 years 6 months ago
CMP design space exploration subject to physical constraints
This paper explores the multi-dimensional design space for chip multiprocessors, exploring the inter-related variables of core count, pipeline depth, superscalar width, L2 cache s...
Yingmin Li, Benjamin C. Lee, David Brooks, Zhigang...
RSP
2003
IEEE
132views Control Systems» more  RSP 2003»
13 years 11 months ago
Rapid Exploration of Pipelined Processors through Automatic Generation of Synthesizable RTL Models
As embedded systems continue to face increasingly higher performance requirements, deeply pipelined processor architectures are being employed to meet desired system performance. ...
Prabhat Mishra, Arun Kejariwal, Nikil Dutt
CORR
2010
Springer
122views Education» more  CORR 2010»
13 years 3 months ago
Two-Way Transmission Capacity of Wireless Ad-hoc Networks
The transmission capacity of an ad-hoc network is the maximum density of active transmitters in an unit area, given an outage constraint at each receiver for a fixed rate of transm...
Rahul Vaze, Kien T. Truong, Steven Weber, Robert W...
CODES
2008
IEEE
14 years 26 days ago
Distributed flit-buffer flow control for networks-on-chip
The combination of flit-buffer flow control methods and latency-insensitive protocols is an effective solution for networks-on-chip (NoC). Since they both rely on backpressure...
Nicola Concer, Michele Petracca, Luca P. Carloni