575 search results - page 10 / 115 » Multi-Valued Logic Synthesis |
80
Voted
ICCAD
1991
IEEE
15 years 1 months ago
1991
IEEE
As feature sizes decrease and chip sizes increase, the area and performance of chips become dominated by the interconnect. In spite of this trend, most existing synthesis systems ...
LOPSTR
2000
Springer
15 years 1 months ago
2000
Springer
In this paper we will present a formal framework, based on the notion of extraction calculus, which has been successfully applied to define procedures for extracting information fr...
247
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DAC
2012
ACM
13 years 5 hour ago
2012
ACM
In this paper we introduce Chisel, a new hardware construction language that supports advanced hardware design using highly parameterized generators and layered domain-specific h...
89
Voted
GLVLSI
2008
IEEE
15 years 4 months ago
2008
IEEE
Timing optimizations during logic synthesis has become a necessary step to achieve timing closure in VLSI designs. This often involves “shortening” all paths found in the circ...
DATE
2010
IEEE
15 years 2 months ago
2010
IEEE
Abstract—We propose a novel synthesis technique for reversible logic based on ant colony optimization (ACO). In our ACO-based approach, reversible logic synthesis is formulated a...