Sciweavers

575 search results - page 14 / 115
» Multi-Valued Logic Synthesis
Sort
View
163
Voted
CAV
2006
Springer
164views Hardware» more  CAV 2006»
15 years 8 months ago
Allen Linear (Interval) Temporal Logic - Translation to LTL and Monitor Synthesis
The relationship between two well established formalisms for temporal reasoning is first investigated, namely between Allen's interval algebra (or Allen's temporal logic,...
Grigore Rosu, Saddek Bensalem
115
Voted
ISPD
2003
ACM
88views Hardware» more  ISPD 2003»
15 years 10 months ago
Synthesis and placement flow for gain-based programmable regular fabrics
In this paper we present the Gain-based Logic Block Array (GLA), a new via-programmable regular fabric. GLA is an array of Gainbased Logic Blocks (GLBs). The GLB is a semi-univers...
Bo Hu, Hailin Jiang, Qinghua Liu, Malgorzata Marek...
145
Voted
DAC
2005
ACM
15 years 7 months ago
Multiplexer restructuring for FPGA implementation cost reduction
This paper presents a novel synthesis algorithm that reduces the area needed for implementing multiplexers on an FPGA by an average of 18%. This is achieved by reducing the number...
Paul Metzgen, Dominic Nancekievill
FPGA
2005
ACM
158views FPGA» more  FPGA 2005»
15 years 10 months ago
Automated synthesis for asynchronous FPGAs
We present an automatic logic synthesis method targeted for highperformance asynchronous FPGA (AFPGA) architectures. Our method transforms sequential programs as well as high-leve...
Song Peng, David Fang, John Teifel, Rajit Manohar
DAC
2006
ACM
16 years 6 months ago
DAG-aware AIG rewriting a fresh look at combinational logic synthesis
This paper presents a technique for preprocessing combinational logic before technology mapping. The technique is based on the representation of combinational logic using And-Inve...
Alan Mishchenko, Satrajit Chatterjee, Robert K. Br...